With recent greater functionality of a mobile terminal and higher density of video contents, a mobile terminal commonly transmits and receives a high quality video the or a large-volume file. In such an environment, the communication terminal is requested to transmit and receive (perform communication of) a large-volume file at high speed to and from a communication terminal of an opponent.
A short range wireless communication using millimeter waves or infrared radiation has gained attention as high speed communication methods. In order to send and receive a file at high speed between communication terminals, it is important to perform data transmission processing or data receipt processing at high speed in each of the communication terminals to prevent occurrence of a decrease in effective speed of a wireless communication to the greatest extent possible.
In a transmission terminal, an application extracts a file from a storage, and the file is transmitted by designating an IP address of the communication terminal of the opponent as a communication device. In a receiving terminal, a communication device receives the file that the opponent's communication device transmitted to the IP address of the receiving terminal, and an application stores the file in the storage.
During transmitting and receiving of such communication terminals, each of CPUs (Central Processing Units) performs read and write processing between the application and the storage and between the application and the communication device, which incurs large amounts of overhead.
For instance a DMA (Direct Memory Access) controller described in connection with Patent Document 1 has hitherto been known as a method for reducing the overhead. FIG. 10 is a block diagram showing a system configuration of a related-art DMA controller. A brief overview of operation of the related-art DMA controller is described by reference to FIG. 10.
As shown in FIG. 10, the DMA controller described in connection with Patent Document 1 includes a CPU 1. ROM (Read Only Memory) 2, a memory controller 3, RAM (Random Access Memory) 4, a DMA controller 5 including a parameter setting FIFO 5a, and an I/O device 6.
The CPU 1 sets an address that shows a location on the RAM 4 where data are stored and a data size in the parameter setting FIFO 5a of the DMA controller 5. The DMA controller 5 DMA-transfers the data from the RAM 4 to the I/O device 6 in accordance with the address and the data size set in the parameter setting FIFO 5a. 
Further, when a certain volume of file is DMA-transferred, the DMA controller 5 notifies the CPU 1 that the certain volume of file was DMA-transferred. The DMA controller thereby DMA-transfers the file between the RAM 4 and the I/O device 6. In this case, the DMA controller is capable of setting in the DMA controller 5 an address and a data size that are required to effect DMA transfer, so that the overhead which will arise during the DMA transfer can be reduced.